Senior Product Manager, Hardware (NPU IP)

Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and hardware is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart-sensor systems to high-performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators in the industry today that can only accelerate a portion of a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code.

Quadric is seeking a Senior Product Manager, Hardware to own the Chimera GPNPU IP roadmap across five tracks — Compute, Efficiency, Scalability, Safety, and Integration. The IP we freeze in 2026 ships in customer silicon in 2027 and 2028. This role sets the feature list for QC and QD, drives architecture freeze decisions, and partners directly with anchor SoC customers on what they need next. You'll work with HW engineering on execution and the CPO on strategy.

This role is based in Burlingame (Hybrid- 3 days), with quarterly travel to Japan, U.S. East Coast, U.S. Midwest, and customer SoC teams worldwide.

Responsibilities

Hardware roadmap. Translate customer requirements, competitive pressure, and architectural constraints into a track-by-track feature list with explicit gating — what ships, what slips, what gets cut.

Architecture freeze. Build the case for contested architecture decisions (e.g., dedicated requant unit vs. wider MAC array), run the tradeoff with the architects, and bring a recommendation to the PSC.

Customer engagement. Named hardware product owner for anchor accounts. Present new features, ingest formal architecture feedback, and convert it into roadmap input.

IP usability. Find what customers are silently working around — API wrappers, glue logic, custom RTL hooks, workaround scripts.

Hardware competitive intelligence. Track Synopsys NPX6, Arm Ethos-U85, Ceva NeuPro-M, VeriSilicon Vivante, and NVIDIA Jetson at the architectural level. Translate competitor moves into specific feature requirements before gaps appear in customer evals.

SoC integration positioning. Decide which integration knobs (AXI4/ACE-Lite, CoreSight, power-domain partitioning, performance counters) are exposed, which are productized, and how they're described in the integration guide.

Functional safety positioning. Sequence FMEDA work, lockstep configurations, and safety-island architecture.